FREE RANGE VHDL – 4.8 Exercises – Solutions- 1 – c

The following VHDL model uses concurrent signal assignment to implement the function

F(A, B, C, D) = (A̅ + B) · (B̅ + C + D̅) · (A̅ + D)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity 1cFunction is
    port (
        A, B, C, D : in  std_logic;
        F          : out std_logic
    );
end entity 1cFunction ;

architecture Concu_Assign_Arch of 1cFunction is
begin
    -- Concurrent signal assignment
    F < = (not A or B) and              -- (A̅ + B)
          (not B or C or not D) and     -- (B̅ + C + D̅)
          (not A or D);                 -- (A̅ + D)

end architecture Concu_Assign_Arch;

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