FREE RANGE VHDL – 4.8 Exercises – Solutions- 2 – b

The following VHDL model uses conditional signal assignment to implement the function
F(A, B, C, D) = (A̅ + B) · (B̅ + C + D̅) · (A̅ + D)
NOTE: Conditional signal assignment allows you to check conditions sequentially and assign the value of F based on the first true condition.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Entity declaration
entity 2b-Function is
    port (
        A, B, C, D : in  std_logic;  -- Input signals A, B, C, D
        F          : out std_logic   -- Output signal F
    );
end entity 2b-Function;

-- Architecture using conditional signal assignment
architecture Cond_Assig_Arch of 2b-Function is
begin
    -- Conditional signal assignment implementing F(A, B, C, D)
    F < = '1' when ((A = '0' or B = '1') and (B = '0' or C = '1' or D = '0') and (A = '0' or D = '1')) else
         '0';
end architecture Cond_Assig_Arch;

The following VHDL model uses selected signal assignment to implement the function
F(A, B, C, D) = (A̅ + B) · (B̅ + C + D̅) · (A̅ + D)
NOTE: Selected signal assignment allows mapping of a combination of inputs to an output in a more direct manner, similar to a case statement!

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity 2b-Function is
    port (
        A, B, C, D : in  std_logic;  -- Input signals A, B, C, D
        F          : out std_logic   -- Output signal F
    );
end entity 2b-Function;

architecture Sele_Assig_Arch of 2b-Function is
    signal term1, term2, term3 : std_logic;
begin
    -- Compute the intermediate terms
    term1 < = not A or B;          -- A' + B
    term2 < = not B or C or not D; -- B' + C + D'
    term3 < = not A or D;          -- A' + D

    -- Use selected signal assignment with intermediate terms
    with (term1 and term2 and term3) select
        F < = '1' when '1',
             '0' when others;
end architecture Sele_Assig_Arch;

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