The 8-input AND gate implemented using a direct concurrent signal assignment, where all the inputs are ANDed together
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AND8 is
port (
A : in std_logic_vector(7 downto 0);
F : out std_logic
);
end entity AND8;
architecture Concu_Assign_Arch of AND8 is
begin
-- Concurrent signal assignment
F < = A(0) and A(1) and A(2) and A(3) and A(4) and A(5) and A(6) and A(7);
end architecture Concu_Assign_Arch ;
The following code is a 8-input AND gate implemented using a direct conditional signal assignment.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AND8 is
port (
A : in std_logic_vector(7 downto 0);
F : out std_logic
);
end entity AND8;
architecture Condi_Assign_Arch of AND8 is
begin
-- Conditional signal assignment
F < = '1' when (A(0) = '1' and A(1) = '1' and A(2) = '1' and A(3) = '1' and
A(4) = '1' and A(5) = '1' and A(6) = '1' and A(7) = '1')
else '0';
end architecture Condi_Assign_Arch;
The following is the Selected Signal Assignment that uses a “with select” statement to assign ‘1’ to F only when the input vector A equals “11111111”. For any other input combination, F is set to ‘0
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AND8 is
port (
A : in std_logic_vector(7 downto 0);
F : out std_logic
);
end entity AND8;
architecture Sele_Assign_Arch of AND8 is
begin
-- Selected signal assignment
with A select
F < = '1' when "11111111", -- All inputs are '1'
'0' when others; -- Any other case
end architecture Sele_Assign_Arch;