This is the model in VHDL using conditional signal assignment of 8:1 multiplexer (MUX) has 8 input signals, 3 selection signals and one output
NOTE; the “case” statement within a “process” block assigns the output based on the value of the selection line “S”
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux8to1_conditional is
Port (
A : in std_logic_vector(7 downto 0); -- 8 inputs
S : in std_logic_vector(2 downto 0); -- 3 select lines
Y : out std_logic -- Output
);
end mux8to1_conditional ;
architecture Behavioral of mux8to1_conditional is
begin
process (A, S)
begin
case S is
when "000" = > Y < = A(0);
when "001" = > Y < = A(1);
when "010" = > Y < = A(2);
when "011" = > Y < = A(3);
when "100" = > Y < = A(4);
when "101" = > Y < = A(5);
when "110" = > Y < = A(6);
when "111" = > Y < = A(7);
when others = > Y < = '0'; -- U value - Default case
end case;
end process;
end Behavioral;
Next is the model in VHDL using selected signal assignment of 8:1 multiplexer (MUX) has 8 input signals, 3 selection signals and one output , we use “with select” statement to choose the output based on the selection signal;
NOTE: SSA method directly maps each possible value of the selection lines “S” to the corresponding input from the std_logic_vector
`A`.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux_8_to_1_selected is
Port (
A : in std_logic_vector(7 downto 0); -- 8 inputs
S : in std_logic_vector(2 downto 0); -- 3 select lines
Y : out std_logic -- Output
);
end mux_8_to_1_selected;
architecture Behavioral of mux_8_to_1_selected is
begin
with S select
Y < = A(0) when "000",
A(1) when "001",
A(2) when "010",
A(3) when "011",
A(4) when "100",
A(5) when "101",
A(6) when "110",
A(7) when "111",
'0' when others; -- Default case
end Behavioral;