free_range_vhdl

4.8 Exercises – Solutions

1- For the following function descriptions, write VHDL models that implement these functions using concurrent signal assignment.

a) F(A, B) = A̅B + A + AB̅

b) F(A, B, C, D) = A̅CD̅ + B̅C + BCD̅

c) F(A, B, C, D) = (A̅ + B) · (B̅ + C + D̅) · (A̅ + D)

d) F(A, B, C, D) = ∏ (3, 2)

e) F(A, B, C) = ∏ (5, 1, 4, 3)

f) F(A, B, C, D) = ∑ (1, 2)


2- For the following function descriptions, write VHDL models that implement these functions using both conditional and selected signal assignment.

a) F(A, B, C, D) = A̅CD̅ + B̅C + BCD̅

b) F(A, B, C, D) = (A̅ + B) · (B̅ + C + D̅) · (A̅ + D)

c) F(A, B, C, D) = ∏ (3, 2)

e) F(A, B, C, D) = ∑ (1, 2)


3- Provide a VHDL model of an 8-input AND gate using concurrent, conditional and selected signal assignment.

4- Provide a VHDL model of an 8-input OR gate using concurrent, conditional and selected signal assignment.

5- Provide a VHDL model of an 8:1 MUX using conditional signal assignment and selected signal assignment.

6- Provide a VHDL model of a 3:8 decoder using conditional signal assignment and selected signal assignment; consider the decoder’s outputs to be active-high.

7- Provide a VHDL model of a 3:8 decoder using conditional signal assignment and selected signal assignment; consider the decoder’s outputs to be active-low.