FREE RANGE VHDL – 4.8 Exercises – Solutions- 1 – e

F(A, B, C) = ∏ (5, 1, 4, 3)
Term 5 (Binary ‘101’) A . B̅ . C
Term 1 (Binary ‘001’) A̅ . B̅ . C
Term 4 (Binary ‘100’) A . B̅ . C̅
Term 3 (Binary ‘011’) A̅ . B . C

The function F will be the logical AND of these terms:
F(A, B, C) = (A . B̅ . C) . (A̅ . B̅ . C) . (A . B̅ . C̅) . (A̅ . B . C)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Entity declaration
entity 1e_Function is
    port (
        A, B, C : in  std_logic;  -- Input signals A, B, C
        F       : out std_logic   -- Output signal F
    );
end entity 1e_Function;

-- Architecture
architecture Con_Logic_Arch of 1e_Function is
begin
    -- Concurrent signal assignment implementing F(A, B, C) = Π(5, 1, 4, 3)
    F < = (not A and not B and C) and    -- term 1 (001)
         (not A and B and C) and        -- term 3 (011)
         (A and not B and not C) and    -- term 4 (100)
         (A and not B and C);           -- term 5 (101)
end architecture Con_Logic_Arch;

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