FREE RANGE VHDL – 4.8 Exercises – Solutions- 6

A 3 to 8 decoder has 3 input signals {which act as the address lines} and 8 output lines. the decoder activates exactly one of the 8 outputs based on the value of the 3 input signals.

Using conditional Signal Assignment, we use a `Process` block to check the value of the input signals and assign the outputs accordingly

NOTE: all outputs are initially set to ‘0’. Then, based on the value of the input vector A, a specific bit in the output vector D is set to ‘1’.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decod3to8_conditional is
    Port (
        A : in  std_logic_vector(2 downto 0);  -- 3 input signals
        D : out std_logic_vector(7 downto 0)  -- 8 output signals
    );
end decod3to8_conditional;

architecture Behavioral of decod3to8_conditional is
begin
    process (A)
    begin
        -- Set all outputs to '0'
        D < = (others = > '0');

        -- Activate one output based on input
        case A is
            when "000" = > D(0) < = '1';
            when "001" = > D(1) < = '1';
            when "010" = > D(2) < = '1';
            when "011" = > D(3) < = '1';
            when "100" = > D(4) < = '1';
            when "101" = > D(5) < = '1';
            when "110" = > D(6) < = '1';
            when "111" = > D(7) < = '1';
            when others = > D < = (others = > '0');  -- Default case
        end case;
    end process;
end Behavioral;

Now a 3 to 8 decoder has 3 input signals and 8 output lines. the decoder activates exactly one of the 8 outputs based on the value of the 3 input signals.


In Selected Signal Assignment, we use the `with … select` construct to directly assign values to the outputs based on the input signal.

NOTE: SSA directly assigns a binary vector to the output D based on the value of the input A and each value of A results in a different output vector, where only one bit is ‘1’ and the rest are ‘0’

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decod3to8_selected is
    Port (
        A : in  std_logic_vector(2 downto 0);  -- 3 input signals
        D : out std_logic_vector(7 downto 0)  -- 8 output signals
    );
end decod3to8_selected;

architecture Behavioral of decod3to8_selected is
begin
    with A select
        D < = "00000001" when "000",
              "00000010" when "001",
              "00000100" when "010",
              "00001000" when "011",
              "00010000" when "100",
              "00100000" when "101",
              "01000000" when "110",
              "10000000" when "111",
              "00000000" when others;  --U value - Default case
end Behavioral;