The 8-input OR gate implemented using a direct concurrent signal assignment.
In concurrent signal assignment, the output is assigned directly based on the input conditions.
library ieee;
use ieee.std_logic_1164.all;
entity or8 is
port (
A: in std_logic_vector(7 downto 0); -- 8-bit input vector
Y: out std_logic -- Output signal
);
end entity or8;
architecture concu_Arch of or8 is
begin
-- Concurrent signal assignment
Y < = A(0) or A(1) or A(2) or A(3) or A(4) or A(5) or A(6) or A(7);
end architecture concu_Arch;
In conditional signal assignment, the output is assigned based on conditions evaluated in order.
library ieee;
use ieee.std_logic_1164.all;
entity or8_conditional is
port (
A: in std_logic_vector(7 downto 0);
Y: out std_logic
);
end entity or8_conditional;
architecture condi_Arch of or8_conditional is
begin
-- Conditional signal assignment
process (A)
begin
if A(0) = '1' or A(1) = '1' or A(2) = '1' or A(3) = '1' or
A(4) = '1' or A(5) = '1' or A(6) = '1' or A(7) = '1' then
Y < = '1';
else
Y < = '0';
end if;
end process;
end architecture condi_Arch;
In selected signal assignment, the output is assigned based on the evaluation of an entire input signal, typically in the form of a “case” statement.
library ieee;
use ieee.std_logic_1164.all;
entity or8_sele is
port (
A: in std_logic_vector(7 downto 0);
Y: out std_logic
);
end entity or8_sele;
architecture sele_arch of or8_sele is
begin
-- Selected signal assignment
with A select
Y < = '1' when "00000001" |
"00000010" |
"00000100" |
"00001000" |
"00010000" |
"00100000" |
"01000000" |
"10000000" |
"11111111",
'0' when others;
end architecture sele_arch;