FREE RANGE VHDL – 4.8 Exercises – Solutions- 7

a 3 to 8 decoder with active-low outputs, the decoder will activate one of the 8 outputs by setting it to ‘0’, while all other outputs will be ‘1’

Using Conditional Signal Assignment let’s set all outputs to `1` initially and then set the selected output to 0 based on the value of the input

NOTE: This method first initialises all outputs to ‘1’. Then uses a case statement to set one specific output to ‘0’ based on the value of the input vector A. This approach is flexible and also can be adjusted for more complex conditions if needed!

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity deco3to8_conditional is
    Port (
        A : in  std_logic_vector(2 downto 0);  -- 3 input signals
        D : out std_logic_vector(7 downto 0)  -- 8 output signals
    );
end deco3to8_conditional;

architecture Behavioral of deco3to8_conditional is
begin
    process (A)
    begin
        -- Set all outputs to '1'
        D <= (others => '1');

        -- Activate one output based on input (set to '0')
        case A is
            when "000" = > D(0) < = '0';
            when "001" = > D(1) < = '0';
            when "010" = > D(2) < = '0';
            when "011" = > D(3) < = '0';
            when "100" = > D(4) < = '0';
            when "101" = > D(5) < = '0';
            when "110" = > D(6) < = '0';
            when "111" = > D(7) < = '0';
            when others = > D < = (others => '1');  -- Default case
        end case;
    end process;
end Behavioral;

Using Selected Signal Assignment we can directly set the output vector D to a value where only one bit is 0 and all others are 1 based on the value of the input A

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity deco3to8_selected is
    Port (
        A : in  std_logic_vector(2 downto 0);  -- 3 input signals
        D : out std_logic_vector(7 downto 0)  -- 8 output signals
    );
end deco3to8_selected;

architecture Behavioral of deco3to8_selected is
begin
    with A select
      D < =  "11111110" when "000", -- Only D(0) is '0', others ar'1'
             "11111101" when "001",  -- Only D(1) is '0', others are'1'
             "11111011" when "010",  -- Only D(2) is '0', others are'1'
             "11110111" when "011",  -- Only D(3) is '0', others are'1'
             "11101111" when "100",  -- Only D(4) is '0', others ar'1'
             "11011111" when "101",  -- Only D(5) is '0', others are'1'
             "10111111" when "110",  -- Only D(6) is '0', others are 1'
             "01111111" when "111",  -- Only D(7) is '0', others are'1'
             "11111111" when others; -- Default case, all outputs are'1'
end Behavioral;