FREE RANGE VHDL – 4.8 Exercises – Solutions- 1 – d

F(A, B, C, D) = ∏ (3, 2)

The product “Π(3,2)” means we take the AND of these two terms.
Term 2 (Binary 0010): A̅ . B̅ . C . D̅
Term 3 (Binary 0011): A̅ . B̅ . C . D

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Entity declaration
entity 1dFunction is
    port (
        A, B, C, D : in  std_logic;  -- Input signals A, B, C, D
        F          : out std_logic   -- Output signal F
    );
end entity 1dFunction;

-- Architecture
architecture Con_Logic_Arch of 1dFunction is
begin
    -- Concurrent signal assignment implementing F(A, B, C, D) = Π(3, 2)
    F < = (not A and not B and C and not D) and  -- term 2
         (not A and not B and C and D);         -- term 3
end architecture Con_Logic_Arch;