FREE RANGE VHDL – 4.8 Exercises – Solutions- 1 – a

The following VHDL model uses concurrent signal assignment to implement the Boolean function

F(A, B) = A̅B + A + AB̅.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Entity declaration
entity 1aFunction is
    port (
        A, B : in  std_logic;  -- Input signals A and B
        F    : out std_logic   -- Output signal F
    );
end entity 1aFunction ;

-- Architecture
architecture Con_Logic_Arch of 1aFunction is
begin
    -- Concurrent signal assignment implementing F(A, B) = A'B + A + AB'
    F < = (not A and B) or A or (A and not B);
end architecture Con_Logic_Arch ;

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