FREE RANGE VHDL – 4.8 Exercises – Solutions- 1 – f

F(A, B, C, D) = ∑ (1, 2)
Term 1 (Binary ‘0001’): A̅ . B̅ . C̅ . D
Term 2 (Binary ‘0010’): A̅ . B̅ . C . D̅

The function F will be the logical OR of these terms:
F(A, B, C, D) = (A̅ . B̅ . C̅ . D) + (A̅ . B̅ . C . D̅)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Entity declaration
entity 1fFunction is
    port (
        A, B, C, D : in  std_logic;  -- Input signals A, B, C, D
        F          : out std_logic   -- Output signal F
    );
end entity 1fFunction;

-- Architecture
architecture Con_Logic_Arch of 1fFunction is
begin
    -- Concurrent signal assignment implementing F(A, B, C, D) = Σ(1, 2)
    F < = (not A and not B and not C and D) or  -- term 1 (0001)
         (not A and not B and C and not D);    -- term 2 (0010)
end architecture Con_Logic_Arch;

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