
The following VHDL model uses conditional signal assignment to implement the function
F(A, B, C, D) = A̅CD̅ + B̅C + BCD̅.
NOTE: Conditional signal assignment allows you to check conditions sequentially and assign the value of F based on the first true condition.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Entity declaration
entity 2a_Cond_Assign is
port (
A, B, C, D : in std_logic; -- Input signals A, B, C, D
F : out std_logic -- Output signal F
);
end entity 2a_Cond_Assign;
-- Architecture using conditional signal assignment
architecture Cond_Assig_Arch of 2a_Cond_Assign is
begin
-- Conditional signal assignment implementing F(A, B, C, D) = A'CD' + BC + BCD'
F < = '1' when (A = '0' and C = '1' and D = '0') else -- A'CD'
'1' when (B = '1' and C = '1' and D = '0') else -- BCD'
'1' when (B = '1' and C = '1') else -- BC
'0'; -- Default case
end architecture Cond_Assig_Arch;
The following VHDL model uses selected signal assignment to implement the function
F(A, B, C, D) = A̅CD̅ + B̅C + BCD̅.
NOTE: Selected signal assignment allows mapping of a combination of inputs to an output in a more direct manner, similar to a case statement!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Entity declaration
entity 2a-Sele_Assign is
port (
A, B, C, D : in std_logic; -- Input signals A, B, C, D
F : out std_logic -- Output signal F
);
end entity 2a-Sele_Assign;
-- Architecture using selected signal assignment
architecture Sele_Assig_Arch of 2a-Sele_Assign is
begin
-- Selected signal assignment implementing F(A, B, C, D) = A'CD' + B'C + BCD'
with (A & B & C & D) select
F < ='1' when "0010", -- A'CD'
'1' when "0110", -- BCD'
'1' when "0001", -- B'C
'0' when others; -- Default case
end architecture Sele_Assig_Arch ;