The following VHDL model uses **conditional signal assignment** to implement the function

F(A, B, C, D) = ∏ (3, 2)

the function F(A, B, C, D) = ∏ (3, 2) corresponds to the **product of max-terms** where F is ‘0’ for the terms 3 and 2.

Term 2: A̅ . B̅ . C . D̅

Term 3: A̅ . B̅ . C . D

This is corresponding to :

F(A, B, C, D) = (A +B +C̅ +D) for term 2

F(A, B, C, D) = (A +B +C̅ +D̅) for term 3

**NOTE**: Conditional signal assignment allows you to check conditions sequentially and assign the value of F based on the first true condition.

```
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity 2cFunction is
port (
A, B, C, D : in std_logic;
F : out std_logic
);
end entity 2cFunction ;
architecture Con_assign_Arch of 2cFunction is
begin
process (A, B, C, D)
begin
if (A = '1') or (B = '1') then
F < = '1';
elsif (C = '0') then
F < ='1';
elsif (D = '1') then
F < ='1';
else
F < = '0';
end if;
end process;
end architecture Con_assign_Arch;
```

The following VHDL model uses **selected signal assignment** to implement the function

F(A, B, C, D) = ∏ (3, 2)**NOTE**: The temp signal is a concatenation of inputs A, B, C, and D. The selected signal assignment is used to explicitly define the output F based on the specific binary combinations corresponding to the minterms 2 and 3

F(A, B, C, D) = (A +B +C̅ +D) — for term 2

F(A, B, C, D) = (A +B +C̅ +D̅) — for term 3

```
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity 2cFunction is
port (
A, B, C, D : in std_logic;
F : out std_logic
);
end entity 2cFunction ;
architecture Sele_assign_Arch of 2cFunction is
signal temp : std_logic_vector(3 downto 0);
begin
temp < = A & B & C & D;
with temp select
F < = '0' when "0010", -- term 2
'0' when "0011", -- term 3
'1' when others;
end architecture Sele_assign_Arch;
```