FREE RANGE VHDL – 4.8 Exercises – Solutions- 2 – d

The following VHDL model uses conditional signal assignment to implement the function
F(A, B, C, D) = ∑ (1, 2)

the function corresponds to the sum of terms where F is ‘1’ for the terms 1 and 2.

Term 1: A̅ , B̅ , C̅ , D

Term 2: A̅ , B̅ , C , D̅

NOTE: Conditional signal assignment allows you to check conditions sequentially and assign the value of F based on the first true condition.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity 2dFunction is
    port (
        A, B, C, D : in  std_logic;
        F          : out std_logic
    );
end entity 2dFunction ;

architecture Con_assign_Arch of 2dFunction is
begin
    process (A, B, C, D)
    begin
        if (A = '0' and B = '0' and C = '0' and D = '1') then
            F < = '1';  -- term 1: A'B'C'D
        elsif (A = '0' and B = '0' and C = '1' and D = '0') then
            F < = '1';  -- term 2: A'B'C D'
        else
            F < = '0';
        end if;
    end process;
end architecture Con_assign_Arch ;

The following VHDL model uses selected signal assignment to implement the function
F(A, B, C, D) = ∑ (1, 2)

The signal ‘temp’ is created by concatenating the inputs A, B, C, and D into a 4-bit vector. The ‘with select’ statement is then used to assign ‘1’ to F for the binary values corresponding to terms 1 and 2, and ‘0’ for all other combinations.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity 2dFunction is
    port (
        A, B, C, D : in  std_logic;
        F          : out std_logic
    );
end entity 2dFunction ;

architecture Sele_assign_Arch of 2dFunction is
    signal temp : std_logic_vector(3 downto 0);
begin
    temp < = A & B & C & D;

    with temp select
        F < = '1' when "0001", -- term 1: A'B'C'D
             '1' when "0010", -- term 2: A'B'CD'
             '0' when others; -- for U value -Default case
end architecture Sele_assign_Arch;