FREE RANGE VHDL – 4.8 Exercises – Solutions- 1 – b

The following VHDL model uses concurrent signal assignment to implement the function

F(A, B, C, D) = A̅CD̅ + B̅C + BCD̅

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity 1bFunction is
    port (
        A, B, C, D : in  std_logic;
        F          : out std_logic
    );
end entity 1bFunction ;

architecture Concu_Assign_Arch of 1bFunction is
begin
    -- Concurrent signal assignment
    F < = (not A and C and not D) or    -- A̅ C D̅
         (not B and C) or              -- B̅ C
         (B and C and not D);          -- B C D̅

end architecture Concu_Assign_Arch ;

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